0.2nm Arrives: New Chip Roadmap Out
The next stage in the development of CMOS transistors (the type used in nearly all chips on Earth) will be complementary field-effect transistors (CFETs). Imec predicts that commercial adoption will begin around 2033. 2 nanometers) around 2041. Let me burst your bubble: N2 does not actually correspond to any physical 2-nanometer feature on the chip.
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The next stage in the development of CMOS transistors (the type used in nearly all chips on Earth) will be complementary field-effect transistors (CFETs). Imec predicts that commercial adoption will begin around 2033.
As the chart below shows, the top row displays chip “nodes,” ranging from the current N2 (“2-nanometer node”) all the way to the A2 node (“2-angstrom node,” where 2 angstroms = 0.2 nanometers) around 2041. Let me burst your bubble: N2 does not actually correspond to any physical 2-nanometer feature on the chip. It’s purely an industry marketing label. These numbers stopped reflecting the actual size of transistors years ago. Of course, some other numbers are still meaningful, and I’ll explain those later. Node names represent generational milestones, with each step promising significant improvements in chip density, performance, and energy efficiency. Every new node brings wave after wave of innovation to the world, some of which may contain the next “killer app” which is the original goal chipmakers pursue.
Imec’s latest roadmap indicates that transistor structures will change starting with the A7 node around 2033. Here’s a guide to interpreting the roadmap:
A7: Industry name for the “7-angstrom” process node. This is just a label; there isn’t necessarily any actual 7-angstrom-long structure in the transistor.CPP: Contacted Poly Pitch — the distance from one transistor to the next, in nanometers.Cell: Cell height — the minimum vertical dimension of a logic cell, in nanometers.4.5T: The number of parallel interconnects (routable lines) that can fit in the smallest logic cell.0.55NA EUV: Extreme ultraviolet lithography using a higher numerical aperture (0.55), which allows it to print finer features than today’s 0.33NA machines.MP: The minimum pitch EUV can produce — the distance between two lines.
