The semiconductor industry is undergoing a major architectural transition: at advanced logic nodes of 3 nm and below, gate-all-around (GAA) nanosheet transistors are replacing FinFETs. GAA nanosheet technology is scalable to the A10 logic layer and supports 5.5-track (T) standard cells, where track count (T) is the metric for standard-cell height.
Driven by the AI revolution, application requirements are becoming increasingly diverse, and the options at the A7 node are multiplying. According to imec’s latest roadmap, one path is to design systems around imec’s CMOS 2.0 scaling paradigm. CMOS 2.0 partitions a system-on-chip (SoC) into heterogeneous functional tiers, each optimized with the most suitable technology and reconnected through 3D interconnects. For other use cases, GAA nanosheet technology can be pushed to its scaling limit, with power delivered from either the front side or the back side. The industry can also transition to a complementary field-effect transistor (CFET) device architecture. By stacking p-type and n-type MOS transistors, standard cells can be further reduced to 3T, extending the conventional CMOS logic roadmap at least to the A3 technology node.
Imec and its industrial partners are working to make CFET-based devices manufacturable. In recent years, they have laid the groundwork for the key integration approaches, which fall into two categories: monolithic CFET (mCFET) and sequential CFET (sCFET).
Both approaches start from vertically stacked Si/SiGe layers, from which n-type and p-type FETs are fabricated. For mCFET, a vertical device structure with shared top and bottom gates is patterned and processed through a sequence of process steps. Patterning, deposition, and selective removal of materials around and between these high-aspect-ratio structures demand substantial effort in module development. By contrast, sCFET uses dedicated masks to pattern the top and bottom devices independently. Individual process steps are simpler than in mCFET, but some critical steps must be performed twice—once for the top device and once for the bottom. sCFET also involves two wafer flips, which induce wafer distortion and challenge the precise alignment of connections between the front and back devices. Until further progress is made in overlay accuracy, mCFET is considered the fastest path to industrial adoption.
