Earlier this year, unveiled the world’s first 0.7-nanometer chip technology. It is based on a newly designed transistor architecture, a nano-stack structure built from layered nanosheets, which breaks through the space limits on how many transistors can be integrated in a given area. In short, it overcomes the Z-axis limitation and redefines how modern logic circuits scale. The result is nearly 100 billion transistors on a 150 mm² chip, almost twice the density of IBM’s 2-nanometer chips, with a 50% performance gain, a 70% improvement in energy efficiency, and a 40% increase in SRAM capacity.
Now, as the semiconductor industry approaches a major change in transistor architecture, IBM has announced plans to release an early-stage research process design kit (PDK) for its 7-angstrom nano-stack technology in the first quarter of 2027. Because semiconductor design is at the dawn of a new era, the PDK is meant to give organizations an early opportunity to explore how this emerging architecture will change their products and services.