AI chips are getting bigger — and hotter.
Over the past few years, the chip industry has invented many ways to keep increasing AI compute. As transistor scaling grew harder, the industry turned to chiplets. When a single die could no longer hold enough logic, CoWoS was used to place multiple compute dies together. When on-chip memory bandwidth was insufficient, more HBM was added. When data movement between chips became the bottleneck, the industry developed NVLink, UALink, and even CPO.
All of these technologies ultimately push the problem toward a physical constraint that is becoming harder and harder to ignore: heat.
At SEMICON Taiwan 2026, TSMC(**) advanced packaging R&D lead James Chen presented a set of figures that were striking. Based on the technology roadmap he disclosed, from 2024 to 2029, **CoWoS package size is expected to grow from about 3.3 reticle sizes to more than 14 reticle sizes; the number of compute transistors in a single package could increase by about 48×, and total HBM bandwidth could rise by more than 34×. Alongside that growth, power consumption of AI systems and advanced packages is rising rapidly. Related information indicates that TSMC expects AI system power to increase by about 6× over the next five years, while power of advanced AI packages will move from hundreds of watts toward roughly the 4.1 kW class.
The AI chip industry is running into an increasingly difficult problem: chips can still be stacked, HBM can still be added, and packages can still be made larger — but how is the heat generated by those transistors supposed to get out? Cooling is shifting from an accessory problem for AI servers into a foundational technology question that will determine whether the next generation of AI chips can keep scaling.
