In modern data center chips, power delivery has become a critical bottleneck limiting performance scaling. The surge in artificial intelligence (AI) and high-performance computing (HPC) workloads is pushing power delivery networks (PDNs) far beyond what traditional designs were built to handle. As current levels rise, resistive losses and voltage droop in the PDN intensify, and incremental improvements are no longer enough. Stacked-die multi-chip architectures make the problem worse by raising effective current density, increasing routing congestion, and adding reliability challenges.
Intel() recently published a white paper examining power-delivery challenges from the accelerator level through the rack and up to the data center. It focuses on how scaling trends are reshaping power requirements across the system hierarchy. The paper does not argue for a single “optimal” power solution. Instead, it outlines a set of technical paths that experienced architects and technologists can apply selectively, based on system requirements and architectural trade-offs.
Power-delivery challenges at the chip
Design trends in chips, servers, and data centers are pushing power delivery toward physical limits. As compute density rises, maintaining robust power integrity (PI) requires optimizing the entire PDN, from the board through the package to the die.
Accelerator package design trends
Modern accelerator packages integrate unprecedented amounts of compute, memory, and interconnect into a single package to meet the performance and bandwidth demands of AI and HPC workloads.
AI accelerators typically run at low supply voltages and need very high current to deliver high power (see Figure 1). As a result, today’s levels of integration require package-level currents on the order of thousands of amperes (kA). These trends create two fundamental power-delivery challenges.
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