AI chips keep getting bigger, and advanced packaging is looking for new ways to produce them.
CoWoS has long been one of the main advanced packaging routes. But as GPU and HBM integration scales up, the limits of traditional wafer-level packaging in area utilization have become more apparent, and the industry is turning to CoPoS (Chip-on-Panel-on-Substrate).
The most visible difference is that the processing carrier changes from a round wafer to a rectangular panel. According to an analysis published on October 22 by Yong-woon Kang, CEO of Infomarket, TSMC is pushing in this direction, and Samsung Electro-Mechanics is also believed to be exploring related technology.
The opportunity extends beyond the packaging process itself into equipment and materials. Infomarket focuses on three types of equipment: 40mm-class thermal compression (TC) bonders, MSVP precision dicing systems, and 120mm-class TC bonders. Further out, as glass-core substrates and glass interposers develop, demand for related equipment could see another round of growth.