According to South Korean media reports, Taiwan’s TSMC() is expected to continue using existing microbump packaging technology for the time being in advanced packaging that combines high-bandwidth memory (HBM) with AI accelerators, rather than switching to hybrid bonding. Given material development cycles, finer microbumps are expected to remain in use through late-generation HBM4 and into early HBM5 products.
According to sources in the materials industry on the 2nd, TSMC has asked its materials and equipment partners to develop 5-micron-class bonding and underfill technology. The goal is to further reduce the size of the microbumps currently used in advanced packaging. Supply chains in South Korea and Japan have already begun R&D, with mass production of 5-micron-class microbumps expected in the second half of the year after next.
At present, the microbump height for third-generation extended HBM (HBM3E) is in the 15–25 μm range, while fourth-generation HBM (HBM4) microbumps are approaching 10 μm. A Japanese materials supplier said quality assurance becomes difficult below 15 μm. 5 μm is even further below that assurance threshold.
The reason for lowering and thinning the bumps is the upper limit on HBM cube height and contact density. Under JEDEC standards, cube height is 775 μm. As the number of I/O contacts increases, height must not exceed this limit.