Advanced packaging technologies have become an indispensable part of high-end CPU and GPU designs. Virtually all of Intel’s high-end client and data center CPUs rely on its Embedded Multi-die Interconnect Bridge (EMIB) and Foveros technologies. But what is the future direction of these two advanced packaging technologies? Before exploring their future development trends, let’s first review where they stand today.
Although Intel’s advanced packaging journey began in 2017 with the Kaby Lake-G CPU and Stratix 10 FPGA, packaging technology was far less popular at the time than it is now. However, Intel and its industry peers have been relentlessly advancing these technologies. As early as 2020, Intel was the first to publish a detailed roadmap for multi-die processors that covered its 2.5D and 3D integration technologies—EMIB and Foveros. After the failure of its initial 10nm process technology, Intel made it clear that its multi-die strategy was a sustainable way to deliver performance and feature enhancements at a cost-effective and predictable pace.
While we cannot say that all of Intel’s() multi-die projects have been successful, it is certain that the vast majority of client and data center CPU products Intel has launched in recent years have adopted multi-die designs and rely on EMIB and Foveros advanced packaging technologies.
