Open any of the latest AI accelerators, and you will find the same pattern: the world’s most expensive chips are assembled from smaller pieces called chiplets. Compute dies sit side by side, surrounded by large amounts of memory. If higher performance is the goal, why not simply make a bigger chip? The answer lies in how chips are printed.
Chips are made by projecting circuit patterns onto a wafer with a lithography scanner. The maximum exposure area is fixed at 26 × 33 mm, or about 858 mm². A chip must fit inside a single exposure field, so 858 mm² is the physical size limit. For years, NVIDIA’s flagship GPUs have been constrained by that limit.
TSMC() has put CoWoS packaging into high-volume production. Its exposure area is 5.5 times that of a conventional package and can hold up to 12 HBM stacks, with reported yields above 98%. At its North America Technology Symposium in April 2026, TSMC published a roadmap showing package size reaching 9.5× in 2027 and 14-field in 2028. TSMC described a 14-field package as roughly 10 large compute dies plus 20 HBM stacks. Photoresist limits the size of a single die; the industry has already broken that limit by assembling multiple dies in one package. That is the direction packaging technology is taking.
