In the past few years, as the large model wave has swept the globe, the computing architecture of data centers has been iterating rapidly. From the early days of stacking general-purpose GPUs to today’s situation where major cloud vendors are entering the fray with custom ASICs, the arms race on the compute side has entered a new phase. But what many people have overlooked is that the more intense the competition around the compute core becomes, the more likely data transmission between chips is to become the bottleneck. The high-speed interconnect technologies buried at the chip’s foundational layer are shifting from supporting roles to core ones.
In June 2025, Qualcomm announced the acquisition of Alphawave Semi, a global leader in high-speed connectivity IP, for approximately $2.4 billion. This move strengthens its SerDes high-speed interface and UCIe die-to-die interconnect technology reserves, while also bringing in Open-Silicon’s full custom ASIC design business. At the end of July 2026, MediaTek CEO Rick Tsai revealed in an earnings call that development of 400G/448G SerDes IP is progressing smoothly, and the full suite of standardized IP resources is expected to complete all verification and be delivered to customers in the second half of 2027, supporting the development of next-generation cloud custom ASIC hardware.
The fact that two companies originally focused on consumer chips are simultaneously ramping up investment in SerDes signals a shift in the underlying logic of the compute hardware track. According to statistics from PW Consulting, the global SerDes IP core market reached $1.41 billion in 2025. By end-user segment, data center and cloud computing scenarios accounted for 49.9%. The market is projected to reach $3.35 billion by 2032, with a compound annual growth rate of approximately 13.15%.
