The Passive Component Industry in 2026: Almost No Segment Is More Talked About Than Silicon Capacitors
In May, ADI announced a $1.5 billion acquisition of silicon capacitor maker Empower Semiconductor. That same month, Samsung Electro-Mechanics signed a KRW 1.557 trillion long-term silicon capacitor supply agreement covering deliveries through 2027–2028—the largest single order since it entered the business. In June, Samsung Electro-Mechanics publicly laid out its commercialization strategy for the first time at a technical seminar in Seoul, with management explicitly positioning silicon capacitors as the “third growth curve” after MLCC and FC-BGA substrates. In August, Chinese silicon capacitor makers successively announced new developments and drew intense industry and capital-market attention.
Meanwhile, reports that NVIDIA’s() next-generation Rubin architecture will treat embedded silicon capacitors as standard equipment have continued to circulate through the supply chain.
A dense sequence of industry events is sending a clear signal: this new class of capacitor, built on silicon wafers with semiconductor processes, is moving from the lab and niche applications onto the center stage of AI compute hardware. As interest rises, debate over whether silicon capacitors will disrupt MLCC has intensified as never before.
Why Silicon Capacitors?
To understand the rise of silicon capacitors, one must first understand the power-delivery crisis facing AI compute chips.
Take NVIDIA GPUs as an example. From GB200 to the next-generation Rubin architecture, MLCC count per board is expected to rise from about 6,500 to nearly 12,000. Doubling power consumption is driving a sharp increase in capacitor demand. The core problem, however, is not quantity but location.
In a traditional board-level power architecture, MLCCs sit on the PCB and feed the chip through relatively long current paths. When transient currents reach thousands of amperes and core voltage falls below 0.8 V, parasitic inductance on that long path severely limits transient response.
A TrendForce report released in June 2026 noted that power-integrity requirements for AI servers are extending from the board into the package. Board-level MLCCs alone can no longer meet the need for independent, fast-response decoupling networks for every die and power domain in multi-chip architectures.
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