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Transistors Beyond 1nm: The Four-Way Race · Storyflo

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Transistors Beyond 1nm: The Four-Way Race

Meng Li · chippub

Oct 25, 2026 · 1 min listen · Last updated October 25, 2026

For two decades, the semiconductor industry has kept pace with Moore’s Law by repeatedly reshaping the transistor: from planar to FinFET, and now to the gate-all-around (GAA) nanosheet structure. Each generation has bought roughly another decade of scaling headroom.

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For two decades, the semiconductor industry has kept pace with Moore’s Law by repeatedly reshaping the transistor: from planar to FinFET, and now to the gate-all-around (GAA) nanosheet structure. Each generation has bought roughly another decade of scaling headroom.

As leading logic chipmakers push nanosheet processes into production, a new transistor architecture, the complementary FET (CFET), has become a focus at IEDM (the International Electron Devices Meeting) and the VLSI Symposium.

Instead of placing n-type and p-type transistors side by side, a CFET stacks them vertically (Figure 1). The core idea is straightforward: a standard CMOS inverter needs one NMOS and one PMOS device laid out next to each other, occupying the corresponding area on the wafer, whereas a CFET stacks them and can, in theory, implement the same logic in about half the horizontal footprint (Figure 2).

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